Area-Efficient Design of Asynchronous Circuits Based on Balsa Framework for Synchronous FPGAs

This paper presents an efficient asynchronous design methodology for synchronous FPGAs. The mixed synchronous/asynchronous design is the best way to minimize the power consumption of a circuit implemented on a synchronous FPGA. For asynchronous circuit synthesis, Balsa was proposed. However, the problem is that circuits synthesized from Balsa description need a lot of logic resources. To solve this problem, we propose two optimization methods for gate-level netlist. First, we introduce an areaefficient C-element suitable for FPGAs. Then, we propose optimization methods for an adder with a carry input and constant adder. The evaluation results show that the proposed method reduces the logic resource consumption by 26% to 47%.